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Edge Security by Design, Part 1
Security is the feature you don’t see until it fails Every edge device is a small vault in someone else’s hands. Your bank card…
8 min read
30 Sep 2026
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Accelerating a RISC-V Processor with a Custom Instruction
How to identify a repeated computation, design a custom Instruction Set Extension, integrate it into a pipelined processor, and measure the speedup up to…
11 min read
20 Aug 2026
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Designing a 5-Stage Pipelined RISC-V Processor from Scratch
A practical walkthrough of building an RV32I pipelined processor in SystemVerilog : from architecture to simulation, with forwarding, hazard detection, and a clear path…
14 min read
06 Aug 2026
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From Silicon to Boot Prompt: Building a Custom Yocto BSP for the Zybo Z7-10
Most Zynq-7000 tutorials stop at PetaLinux. Xilinx’s own tooling wraps Yocto in a friendly CLI, generates your BSP for you, and mostly just works…
6 min read
09 Jul 2026
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Designing Google’s TPU Hardware Accelerator: From Neural Network Math to RTL Design
A complete guide to building a systolic neural network inference engine with Zynq SoC. Google’s Tensor Processing Unit changed how the world thinks about…
17 min read
24 Apr 2026
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Building Efficient Neural Networks for FPGAs: Part 2
Running ML inference on an Artix-7 or Kintex FPGA without a hard processor using a MicroBlaze soft CPU to drive an hls4ml accelerator. Part…
8 min read
08 Mar 2026